I2C Implementation for LabVIEW FPGA
This code was originally designed in 2005 and has been maintained for in-circuit functional testing of I2C EEPROM chips. Since the code implements the three basic sequence formats: Master-to-Slave Write, Master-Slave Read, or a combined Master-to-Slave Write with Read sequence it can be used with almost any I2C IC.
HDLC Implementation for LabVIEW FPGA
This code was originally designed for functional testing of a customer’s product that had a proprietary interface. The code was simplified and posted as a reference for individuals that might be interested in attempting to implement their own version of HDLC or even SDLC.